As the complexity of VLSI devices increases, the complexity of testing these devices in a production environment also increases. Testers have evolved which provide sub-nanosecond accuracies for generating and distributing high speed waveform edges to boards of up to 256 tester pins and having the edges all arrive at the pins at precisely the same instant. However, there are still a number of inaccuracies due to multi-error sources that are inherent in the system.
One of the more critical specifications of a tester is the timing system. At present, some systems provide a 60-ps resolution, 500-ps maximum driver-to-driver and comparator-to-comparator skewing, and 700-ps maximum edge placement error. The overall timing accuracy is within .+-.1.5 nanoseconds. Actual testing with these inherent errors can result in increased measurement error. Design of the VLSI testers is made more difficult by the requirement of maintaining timing accuracy across all the tester pins, especailly when the number of pins is increased to upwards of 256 pins.
Sources of the more complex VLSI testers require very sophisticated calibration techniques. It is necessary through calibration to ensure that all timed voltage transitions delivered to the pins of the device under test (DUT), and at all times at which data output from the device is compared with expected data, are accurate in relation to a defined reference. The degree of this accuracy can determine the overall system accuracy. Signals traveling a channel path to a DUT must pass through multiplexers, formatters, cables and drivers or detectors. Timing variations are inherent in these circuits, and the associated cable lengths from channel to channel. These voltage transitions at the input pins and data detection at the output pins occur at different times even though they are supposed to be coincident when programmed with like delays. These timing variations are called "skew". Basically, calibration determines or measures skewing in each system channel and compensates for it by means of a variable delay in each system input and output channel. Hardware, software or a combination of the two, can be used to control the compensating delay.
In hardware calibration, normal techniques involve either torque adjustments or premeasured cables. In the torque adjustment method, channel delays are measured and then hardware delays are adjusted. When premeasured cables are utilized, a measurement is first made and then a cable of an appropriate length placed in each channel path to make all delays equal. However, these manual methods are time consuming, and cannot account for errors due to environmental, electrical and time induced circuit drifts while on-line testing is in process.
An automatic calibration scheme can be implemented with the use of a switch matrix, which can be built into a device interface board, to connect each of the system input driver channels to a reference detector. Each of the driver delays is adjusted to this reference detector. Then, each channel detector is excited by the associated driver and calibrated with respect to the system strobe. This method has two problems; first, the switching matrix must be "manually" substituted and second, a quality 1 to N matrix is very bulky and expensive to build because of the difficulty in eliminating switching stubs, which upset the characteristic impedance of the cable interconnect scheme.
Another automatic calibration technique utilizes time domain reflectometry (TDR). TDR is based on transmission line theory wherein a wave traveling through a transmission line terminated by anything other than the lines characteristic impedance is reflected back through the line. If the line terminates with an open circuit, the reflected waves ambient equals that of the forward wave. A number of these circuits have been utilized by such companies as Teradyne, which provides an automatic edge lock technique utilizing TDR to measure channel delays. This approach however, provides some disadvantages in that it is rather complex and expensive, requiring a computer controlled TDR, a 1 to N switching matrix and bypass switches for the pin electronics drivers. A binary matrix of 1 to 256 would require eight levels of form C relays, each of which have a built-in stub.